The present invention relates to a data storage apparatus and, more particularly, to a flash memory data storage apparatus including a NAND-type flash memory.
There continues to be an increasing demand for nonvolatile memory devices capable of being electronically programmed and erased, and which can retain data despite removal of a power supply. In particular, NAND-type flash memories are widely used as storage devices for music, photographs, and so forth, because they are able to store a large number of data in a given chip size.
Meanwhile, as many computer users continue to require a ever-faster system operation, the standard for system operating speed (or frequency) of a computer has become graded up to about a 10 ns operation cycle. However, standard NAND-type flash memories have data access cycles on the order of 80 ns due to the cycle time consumed by the control for data lines during program and read operations. For this reason, it has been difficult to for data storage apparatus containing such NAND-type flash memory devices to have operation cycles that correspond with those of external systems.
In order to address this limitation, techniques have been proposed in which buffer memory is embedded in a flash memory data storage apparatus. In such a case, the buffer memory stores data belonging to one page of a flash memory. While data of a page of the buffer memory is provided for use by the external system, data of another page is transferred to the buffer memory from the flash memory. This approach leads to improved data transmission speed (i.e., data rate) between the external system and the flash memory data storage apparatus to a certain degree.
However, since the data rate between the flash memory and the buffer memory is still relatively low, the resulting system is generally insufficient for meeting user demand for data transmission speed (i.e., data rate) between an external system and the flash memory data storage apparatus in modern systems.